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ISL6314
Data Sheet March 30, 2007 FN6455.0
Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications
The ISL6314 single-phase PWM control IC provides a precision voltage regulation system for advanced microprocessors. This controller IC maintains the same features as the multi-phase product family, but reduces the output to a single-phase, for lower current systems. By reducing the number of external parts, this integration is optimized for a cost and space saving power management solution. One outstanding feature of this controller IC is its multiprocessor compatibility, allowing it to work with both Intel and AMD microprocessors. Included are programmable VID codes for Intel VR11 as well as AMD 5-bit and 6-bit DAC tables. A circuit is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be positively or negatively offset through the use of a single external resistor. Another unique feature of the ISL6314 is the addition of a circuit that allows optimizing compensation to be added for flatter load transient response and well controlled dynamic VID response. The ISL6314 also includes advanced control loop features for optimal transient response to load apply and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for load line programming. Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) are two other unique features, allowing for quicker initial response to high di/dt load transients; the number of output bulk capacitors can be reduced, helping to reduce cost. Protection features of this controller IC include a set of sophisticated overvoltage, undervoltage, and overcurrent protection. Furthermore, the ISL6314 includes protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the microprocessor and power system.
Features
* Integrated-driver Single-Phase Power Conversion * Precision Core Voltage Regulation - Differential Remote Voltage Sensing - 0.5% System Accuracy Over-Temperature - Adjustable Reference-Voltage Offset * Optimal Transient Response - Adaptive Phase Alignment (APA) - Active Pulse Positioning (APP) Modulation * Fully Differential, Continuous DCR Current Sensing - Accurate Load Line Programming * Variable Gate Drive Bias: 5V to 12V * Multi-Processor Compatible - Intel VR11 Mode of Operation - AMD Mode of Operation * Microprocessor Voltage Identification Inputs - 8-Bit DAC - Selectable between Intel VR11, AMD 5-bit, and AMD 6-bit DAC tables - Dynamic VID Technology * Overcurrent Protection * Multi-tiered Overvoltage Protection * Digital Soft-Start * Selectable Operation Frequency up to 1.0MHz * Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER* (Note) ISL6314CRZ ISL6314IRZ PART MARKING ISL6314 CRZ ISL6314 IRZ TEMP. RANGE (C) 0 to +70 PACKAGE (Pb-free) PKG. DWG. #
32 Ld 5x5 QFN L32.5x5B
-40 to +85 32 Ld 5x5 QFN L32.5x5B
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "-T" suffix for tape and reel.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6314 Pinout
ISL6314 (32 LD QFN) TOP VIEW
VID0 VID1 VID2 VID3 VID4 VID5 26 VID7 VID6 25 24 PHASE 23 UGATE 22 BOOT 33 GND 21 LGATE 20 NC(TBD) 19 PVCC 18 VCC 17 EN 9 FB 10 VDIFF 11 RGND 12 VSEN 13 OCSET 14 ISENO 15 ISEN16 ISEN+
32 PGOOD SS FS REF OFS APA COMP DVC 1 2 3 4 5 6 7 8
31
30
29
28
27
ISL6314 Integrated Driver Block Diagram
PVCC BOOT
UGATE
PWM GATE CONTROL LOGIC SHOOTTHROUGH PROTECTION
20k
PHASE
SOFT-START AND FAULT LOGIC
10k
LGATE
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ISL6314 Block Diagram
ISENO OCSET PGOOD EN
ISENISEN+ ISEN AMP RGND VSEN OC
100A
x1
FSD
VDIFF 0.85V OPEN SENSE LINE DETECT
UNDERVOLTAGE DETECTION LOGIC
SOFT-START AND FAULT LOGIC POWER-ON RESET VCC PVCC
OVERVOLTAGE DETECTION LOGIC
FS
FS / DROOP SELECT
FSD
BOOT SS MODE / DAC SELECT MOSFET DRIVER UGATE PHASE LGATE DYNAMIC VID D/A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 DVC x2 100A REF E/A FB COMP APA OFS OFFSET ADAPTIVE PHASE ALLIGNMENT CIRCUITRY PWM 2k CLOCK AND MODULATOR WAVEFORM GENERATOR
GND
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ISL6314 Typical Application - ISL6314
FB
DVC VDIFF VSEN
RGND
COMP
APA
+5V VCC
OFS FS REF PVCC +12V
BOOT SS UGATE PHASE ISL6314 LGATE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 LOAD
PGOOD
EN
GND ISEN+ OCSET ISENO ROCSET CCOMP Rs RCOMP ISEN-
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ISL6314 Typical Application - ISL6314 with NTC Thermal Compensation
FB
DVC VDIFF VSEN
RGND
COMP
APA
+5V VCC
OFS FS REF PVCC +12V
BOOT SS UGATE PHASE ISL6314 LGATE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
PLACE IN CLOSE PROXIMITY
NTC LOAD
PGOOD
EN
GND ISEN+ OCSET ISENO ROCSET ISENRs RCOMP CCOMP
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Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V Absolute Boot Voltage, VBOOT . . . . . . . . GND - 0.3V to GND + 36V Phase Voltage, VPHASE . . . . . . . GND - 0.3V to 15V (PVCC = 12V) GND - 8V (<400ns, 20J) to 24V (<200ns, VBOOT - PHASE = 12V) Upper Gate Voltage, VUGATE . . . . VPHASE - 0.3V to VBOOT + 0.3V VPHASE - 3.5V (<100ns Pulse Width, 2J) to VBOOT + 0.3V Lower Gate Voltage, VLGATE. . . . . . . . GND - 0.3V to PVCC + 0.3V GND - 5V (<100ns Pulse Width, 2J) to PVCC+ 0.3V Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) QFN Package (Notes 1, 2) . . . . . . . . . . 32 3.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V 5% Ambient Temperature (ISL6314CRZ) . . . . . . . . . . . . . 0C to +70C Ambient Temperature (ISL6314IRZ) . . . . . . . . . . . . .-40C to +85C
CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER BIAS SUPPLIES Input Bias Supply Current
Recommended Operating Conditions, Unless Otherwise Specified. TEST CONDITIONS MIN TYP MAX UNITS
IVCC; VCC = 5V; EN = high, not switching; IPVCC; PVCC = 12V; EN = high, high, not switching VCC rising VCC falling
9 1 4.25 3.75 4.25 3.75
11.4 2 4.38 3.88 4.38 3.88
16 4 4.50 4.00 4.50 4.00
mA mA V V V V
Gate Drive Bias Current - PVCC Pin VCC POR (Power-On Reset) Threshold
PVCC POR (Power-On Reset) Threshold
PVCC rising PVCC falling
PWM MODULATOR Oscillator Frequency Accuracy, fSW (ISL6314CRZ) Oscillator Frequency Accuracy, fSW (ISL6314IRZ) Adjustment Range of Switching Frequency Oscillator Ramp Amplitude, VP-P CONTROL THRESHOLDS EN Rising Threshold EN Hysteresis REFERENCE AND DAC System Accuracy (1.000V to 1.600V) System Accuracy (0.600V to 1.000V) System Accuracy (0.375V to 0.600V) VIDx Input Low Voltage (INTEL) pins VID0 to VID7 -0.5 -1.0 -2.0 0.5 1.0 2.0 0.4 % % % V 0.84 0.86 110 0.88 V mV RT = 100k ( 0.1%) RT = 100k ( 0.1%) (Note 3) (Note 3) 225 215 0.08 250 250 1.50 275 280 1.0 kHz kHz MHz V
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Electrical Specifications
PARAMETER VIDx Input High Voltage (INTEL) VIDx Input Low Voltage (AMD) VIDx Input High Voltage (AMD) VIDx Pull-Up current (INTEL) VIDx Pull-Down current (AMD) PIN-ADJUSTABLE OFFSET OFS Sink Current Accuracy (Negative Offset) OFS Source Current Accuracy (Positive Offset) ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate Maximum Output Voltage Minimum Output Voltage SOFT-START RAMP Soft-Start Ramp Rate VR11, RSS = 100k AMD, RSS = 100k Adjustment Range of Soft-Start Ramp Rate (Note 3) OVERCURRENT PROTECTION OCSET trip current (ISL6314CRZ) OCSET trip current (ISL6314IRZ) OCSET Accuracy ISENO Offset PROTECTION Undervoltage Threshold Undervoltage Hysteresis Overvoltage Threshold During Soft-Start Overvoltage Threshold (Default) VSEN falling VSEN rising VR11 and AMD VR11, VSEN rising AMD, VSEN rising Overvoltage Hysteresis PGOOD output sink current VSEN falling PGOOD = 0.4V VDAC - 325 1.24 VDAC + 150mV VDAC + 200mV VDAC - 350mV 100 1.27 VDAC + 175mV VDAC + 225mV 100 7.5 VDAC - 375 1.30 VDAC + 200mV VDAC + 250mV V mV V V V mV mA OCSET and ISUM Difference 94 93 -5 -1.7 100 100 0 0 106 107 5 1.7 A A mV mV 0.156 1.25 1.25 6.25 mV/s mV/s mV/s RL = 10k to ground, (Note 3) CL = 100pF, RL = 10k to ground, (Note 3) CL = 100pF, load = 400A, (Note 3) Load = 1mA Load = -1mA 3.90 96 40 20 4.20 1.20 1.4 dB MHz V/s V V ROFS = 32.4k from OFS to VCC ROFS = 6.04k from OFS to GND 47.0 47.0 49.4 49.7 53.0 53.0 A A Recommended Operating Conditions, Unless Otherwise Specified. (Continued) TEST CONDITIONS pins VID0 to VID7 pins VID0 to VID7 pins VID0 to VID7 pins VID0 to VID7; VIDx = 0V pins VID0 to VID7; VIDx = 0.5V MIN 0.8 1.4 TYP -40 20 MAX 0.8 UNITS V V V A A
OVER TEMPERATURE SHUTDOWN (Note 3) Thermal Shutdown Setpoint Thermal Recovery Setpoint SWITCHING TIME (Note 3) UGATE Rise Time tRUGATE; VPVCC = 12V, 3nF load, 10% to 90% 26 ns 160 100 C C
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Electrical Specifications
PARAMETER LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-On Non-Overlap LGATE Turn-On Non-Overlap GATE DRIVE RESISTANCE (Note 3) Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance NOTE: 3. Parameter magnitude guaranteed by design. Not 100% tested. VPVCC = 12V, 15mA source current VPVCC = 12V, 15mA sink current VPVCC = 12V, 15mA source current VPVCC = 12V, 15mA sink current 1.25 0.9 0.85 0.60 2.0 1.65 1.25 0.80 3.0 3.0 2.2 1.35 Recommended Operating Conditions, Unless Otherwise Specified. (Continued) TEST CONDITIONS tRLGATE; VPVCC = 12V, 3nF load, 10% to 90% tFUGATE; VPVCC = 12V, 3nF load, 90% to 10% tFLGATE; VPVCC = 12V, 3nF load, 90% to 10% tPDHUGATE; VPVCC = 12V, 3nF load, adaptive tPDHLGATE; VPVCC = 12V, 3nF load, adaptive MIN TYP 18 18 12 10 10 MAX UNITS ns ns ns ns ns
Timing Diagram
tPDHUGATE tRUGATE UGATE LGATE tFUGATE
tFLGATE tPDHLGATE
tRLGATE
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ISL6314 Functional Pin Description
VCC (Pin 18)
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1F ceramic capacitor.
FB and COMP (Pins 9, 7)
These pins are the internal error amplifier inverting input and output respectively. The FB pin, COMP pin, and the VDIFF pins are tied together through external R-C networks to compensate the regulator.
PVCC (Pin 19)
This pin is the power supply pin for the channel MOSFET drivers, and can be connected to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality 1.0F ceramic capacitor.
DVC (Pin 8)
A series resistor and capacitor can be connected from the DVC pin to the FB pin to compensate and smooth dynamic VID transitions.
OCSET (Pin 13)
This is the overcurrent set pin. Placing a resistor from OCSET pin to ISENO allows a 100A current to flow out of this pin, producing a voltage reference. Internal circuitry compares the voltage at OCSET to the voltage at ISEN-, and if ISEN- ever exceeds OCSET, the overcurrent protection activates.
GND (Pin 33 = metal pad)
GND is the bias and reference ground for the IC, connected to the metal pad under the IC.
EN (Pin 17)
This pin is a threshold-sensitive (approximately 0.85V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation.
APA (Pin 6)
This is the Adaptive Phase Alignment set pin. A 100A current flows out the APA pin and by tieing a resistor from this pin to COMP the trip level for the Adaptive Phase Alignment circuitry can be set.
FS (Pin 3)
A resistor, RT, tied to this pin sets the channel switching frequency of the controller. Refer to Equation 42 for proper resistor calculation. The FS pin also controls whether the droop voltage (as described under pins ISENO, ISEN-, ISEN+) is added to the differential remote-sense amplifier's output (VDIFF). Tieing the RT resistor to ground connects droop voltage, allowing the converter to incorporate output voltage droop proportional to the output current. Tieing the RT resistor to VCC disconnects the droop voltage.
REF (Pin 4)
The REF input pin is the positive input of the error amplifier. It is internally connected to the DAC output through a 2k resistor. A capacitor is used between the REF pin and ground to smooth the voltage transition during soft-start and Dynamic VID transitions. This pin can also be returned to RGND if desired.
NC(TBD) (Pin 20)
This pin is presently NC (No Connect), but is reserved for a future function.
VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7 (Pins 31, 30, 29, 28, 27, 26, 25, 32)
These are the inputs for the internal DAC that provide the reference voltage for output regulation. These pins respond to TTL logic thresholds. These pins are internally pulled high, to approximately 1.2V, by 40A internal current sources for Intel modes of operation, and pulled low by 20A internal current sources for AMD modes of operation. The internal pull-up current decreases to 0 as the VID voltage approaches the internal pull-up voltage. All VID pins are compatible with external pull-up voltages not exceeding the IC's bias voltage (VCC).
OFS (Pin 5)
The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VDIFF. The offset current is generated via an external resistor and precision internal voltage references. The polarity is selected by connecting the resistor to GND (for positive offset) or to VCC (for negative offset). For no offset, the OFS pin should be left unconnected.
UGATE (Pin 23)
Connect this pin to the corresponding upper MOSFET gate. This pin is used to control the upper MOSFET and is monitored for shoot-through prevention purposes.
VSEN (Pin 12)
This pin senses the microprocessor's CORE voltage. Connect this pin to the CORE voltage sense pin or point of the microprocessor.
BOOT (Pin 22)
This pin provides the bias voltage for the upper MOSFET drive. Connect this pin to appropriately-chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pin provides the necessary bootstrap charge.
RGND (Pin 11)
This pin senses the local ground voltage of the microprocessor. Connect this pin to the Ground sense pin or point of the microprocessor. 9
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PHASE (Pin 24)
Connect this pin to the source of the upper MOSFET. This pin is the return path for the upper MOSFET drive.
Operation
Power Conversion
The ISL6314 controller helps simplify implementation by integrating vital functions and requiring minimal external components. The "Block Diagram" on page 3 provides a top level view of the single-phase power conversion using the ISL6314 controller.
LGATE (Pin 21)
This pin is used to control the lower MOSFET. Connect this pin to the lower MOSFET gate.
SS (Pin 2)
A resistor, RSS, placed from SS to VCC or GND will set the soft-start ramp slope. Refer to Equations 16 and 17 for proper resistor calculation. The state of the SS pin also selects which of the available DAC tables will be used to decode the VID inputs and puts the controller into the corresponding mode of operation. For Intel VR11 mode of operation the RSS resistor should be tied to GND. AMD compliance is selected if the RSS resistor is tied to VCC (once in AMD mode, the VID7 bit selects 5-bit DAC if set to a logic high, or 6-bit DAC if set to a logic low).
IL, 7A/DIV
PGOOD (Pin 1)
For Intel mode of operation, PGOOD indicates whether VSEN is within specified overvoltage and undervoltage limits after a fixed delay from the end of soft-start. If VSEN exceeds these limits, or if an overcurrent event occurs, or if the part is disabled, PGOOD is pulled low. PGOOD is always low prior to the end of soft-start. For AMD modes of operation, PGOOD will always be high as long as VSEN is within the specified undervoltage/overvoltage window and soft-start has ended. PGOOD only goes low if VSEN is outside this window.
PWM, 5V/DIV 1s/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 1-PHASE CONVERTER
Output Ripple
Figure 1 illustrates the output ripple. The PWM current forms the AC ripple current and the DC load current. The peak-topeak current about 7A, and the DC components of the inductor current feeds the load. To understand the ripple current amplitude, examine Equation 1 representing a single channel peak-to-peak inductor current.
( V IN - V OUT ) V OUT I PP = --------------------------------------------------------L fS V
IN
ISENO, ISEN-, and ISEN+ (Pins 14, 15, 16)
ISEN-, ISEN+, and ISENO are the DCR current sense amplifier's negative input, positive input, and output respectively. For accurate DCR current sensing, connect a resistor from the phase node to ISEN- and connect ISEN+ to the output inductor, roughly VOUT. A parallel R-C feedback circuit connected between ISEN- and ISENO will then create a voltage from ISEN+ to ISENO proportional to the voltage drop across the inductor DCR. This voltage is referred to as the droop voltage and is added to the differential remotesense amplifier's output. An optional 0.001F to 0.01F ceramic capacitor can be placed from the ISEN+ pin to the ISEN- pin to help reduce common mode noise that might be introduced by the layout.
(EQ. 1)
In Equation 1, VIN and VOUT are the input and output voltages respectively, L is the single-channel inductor value, and fS is the switching frequency. The output capacitors conduct the ripple component of the inductor current. Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. Equation 2 shows the approximation for the output voltage ripple.
V PP = I PP ESR (EQ. 2)
VDIFF (Pin 10)
VDIFF is the output of the differential remote-sense amplifier. The voltage on this pin is equal to the difference between VSEN and RGND (VOUT) added to the difference between ISEN+ and ISENO (droop). VDIFF therefore represents the VOUT voltage plus the droop voltage. The state of the FS pin determines whether the droop voltage is added or not.
Adaptive Phase Alignment (APA)
To improve the transient response, the ISL6314 implements Intersil's proprietary Adaptive Phase Alignment (APA) technique, which turns on the channel during large current step transient events.
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The PWM output state is driven by the position of the error amplifier output signal, VCOMP, as illustrated in Figure 3. At the beginning of each PWM time interval, this VCOMP signal is compared to the internal modulator waveform. As long as the VCOMP voltage is lower then the modulator waveform voltage, the PWM signal is commanded low. The internal MOSFET driver detects the low state of the PWM signal and turns off the upper MOSFET and turns on the lower synchronous MOSFET. When the VCOMP voltage crosses the modulator ramp, the PWM output transitions high, turning off the synchronous MOSFET and turning on the upper MOSFET. The PWM signal will remain high until the VCOMP voltage crosses the modulator ramp again. When this occurs the PWM signal will transition low again. During each PWM time interval the PWM signal can only transition high once. Once PWM transitions high it can not transition high again until the beginning of the next PWM time interval. This prevents the occurrence of double PWM pulses occurring during a single period.
VCOMP MODULATOR RAMP WAVEFORM + PWM TO GATE CONTROL LOGIC
EXTERNAL CIRCUIT APA
ISL6314 INTERNAL CIRCUIT
100A
CAPA
RAPA
VAPA,TRIP LOW PASS FILTER ERROR AMPLIFIER + + COMP
FIGURE 2. ADAPTIVE PHASE ALIGNMENT DETECTION
As Figure 2 shows, the APA circuitry works by monitoring the voltage on the APA pin and comparing it to a filtered copy of the voltage on the COMP pin. The voltage on the APA pin is a copy of the COMP pin voltage that has been negatively offset. If the APA pin exceeds the filtered COMP pin voltage an APA event occurs and the channel is forced on. The APA trip level is the amount of DC offset between the COMP pin and the APA pin. This is the voltage excursion that the APA and COMP pin must have during a transient event to activate the Adaptive Phase Alignment circuitry. This APA trip level is set through a resistor, RAPA, that connects from the APA pin to the COMP pin. A 100A current flows across RAPA into the APA pin to set the APA trip level as described in Equation 3 below. An APA trip level of 500mV is recommended for most applications. A 1000pF capacitor, CAPA, should also be placed across the RAPA resistor to help with noise immunity.
V APA, TRIP = R APA 100 x 10
-6
Active Pulse Positioning (APP) Modulated PWM Operation
The ISL6314 uses a proprietary Active Pulse Positioning (APP) modulation scheme to control the internal PWM signals that command each channel's driver to turn their upper and lower MOSFETs on and off. The time interval in which a PWM signal can occur is generated by an internal clock, whose cycle time is the inverse of the switching frequency set by the resistor connected to the FS pin. The advantage of Intersil's proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal has transitioned high. This is important because is allows the controller to quickly respond to output voltage drops associated with current load spikes, while avoiding the ring back affects associated with other modulation schemes.
-
+ APA TO APA CIRCUITRY
FIGURE 3. CHANNEL PWM FUNCTION
Output Voltage Setting
The ISL6314 uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at the VID pins. The DAC decodes the logic signals into one of the discrete voltages shown in Tables 2, 3 or 4. In the Intel VR11 mode of operation, each VID pin is pulled up to an internal 1.2V voltage by a weak current source (40A), which decreases to 0A as the voltage at the VID pin varies from 0 to the internal 1.2V pull-up voltage. In AMD modes of operation the VID pins are pulled low by a weak 20A current source. External pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5V. The ISL6314 accommodates three different DAC ranges: Intel VR11, AMD K8/K9 5-bit, and AMD 6-bit. The state of the SS and VID7 pins decide which DAC version is active. Refer to Table 1 for a description of how to select the desired DAC version.
.
(EQ. 3)
TABLE 1. ISL6314 DAC SELECT and FUNCTION TABLE DAC VERSION INTEL VR11 AMD 5-BIT AMD 6-BIT SS PIN RSS resistor tied to GND RSS resistor tied to VCC RSS resistor tied to VCC VID7 PIN high low
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TABLE 1. ISL6314 DAC SELECT and FUNCTION TABLE DAC VERSION TIE RESISTOR to VCC RSS: AMD Tables ROFS: Negative RT: No Droop SS PIN OPEN no Offset VID7 PIN TIE RESISTOR to GND RSS: Intel Table ROFS: Positive RT: Droop TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250
TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250
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TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250
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TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued) VID7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID5 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 VDAC 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION CODES VID4 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550
TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION CODES VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VDAC 1.5500 1.5250 1.5000 1.4750 1.4500 1.4250 1.4000 1.3750 1.3500 1.3250 1.3000 1.2750 1.2500 1.2250
TABLE 3. AMD 5-BIT VOLTAGE IDENTIFICATION CODES VID4 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 VID2 1 1 1 1 0 0 0 0 1 VID1 1 1 0 0 1 1 0 0 1 VID0 1 0 1 0 1 0 1 0 1 VDAC Off 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975
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TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION CODES VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VDAC 1.2000 1.1750 1.1500 1.1250 1.1000 1.0750 1.0500 1.0250 1.0000 0.9750 0.9500 0.9250 0.9000 0.8750 0.8500 0.8250 0.8000 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION CODES VID5 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 VID3 0 0 1 1 1 1 1 1 1 1 VID2 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 VDAC 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750
Voltage Regulation
In order to regulate the output voltage to a specified level, the ISL6314 uses the integrating compensation network shown in Figure 4. This compensation network insures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6314 to include the combined tolerances of each of these elements. The ISL6314 incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point, resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the non-inverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The droop voltage, VDROOP, also feeds into the remote-sense amplifier. The remote-sense output, VDIFF, is therefore equal to the sum of the output voltage, VOUT, and the droop voltage. VDIFF is connected to the inverting input of the error amplifier through an external resistor.
V OUT = V REF - V OFS - V DROOP (EQ. 4)
The output of the error amplifier, VCOMP, is compared to the sawtooth waveform to generate the PWM signal. The PWM signal controls the timing of the Internal MOSFET drivers and regulates the converter output so that the voltage at FB is equal to the voltage at REF. This will regulate the output voltage to be equal to Equation 4. The internal and external
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circuitry that controls voltage regulation is illustrated in Figure 4.
EXTERNAL CIRCUIT RC CC COMP ISL6314 INTERNAL CIRCUIT PHASE VID DAC 2k REF CREF FB RFB + VOFS + + VCOMP ISENRS
down so that a larger positive spike can be sustained without crossing the upper specification limit.
L DCR VOUT COUT VL(s) + IOUT
INDUCTOR I L
ERROR AMPLIFIER IOFS VDIFF ISENO
CCOMP
RCOMP
VDROOP + ISEN+ (optional)
VSEN + VOUT RGND + + ISL6314
FIGURE 5. DCR SENSING CONFIGURATION
ISEN+ + VDROOP ISENO DIFFERENTIAL REMOTE-SENSE AMPLIFIER
FIGURE 4. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a preciselycontrolled output resistance. This dependence of output voltage on load current is often termed "droop" or "load line" regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load-current demand changes. The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted
As shown in Figure 5, a voltage, VDROOP, proportional to the current in the channel, IOUT, feeds into the differential remote-sense amplifier. The resulting voltage at the output of the remote-sense amplifier is the sum of the output voltage and the droop voltage. As Equation 5 shows, feeding this voltage into the compensation network causes the regulator to adjust the output voltage so that it's equal to the reference voltage minus the droop voltage. The droop voltage, VDROOP, is created by sensing the current through the output inductors. This is accomplished by using a continuous DCR current sensing method. Inductor windings have a characteristic distributed resistance or DCR (Direct Current Resistance). For simplicity, the inductor DCR is considered as a separate lumped quantity, as shown in Figure 5. The channel current, IL, flowing through the inductor, passes through the DCR. Equation 5 shows the S-domain equivalent voltage, VL, across the inductor.
V L ( s ) = I L ( s L + DCR ) (EQ. 5)
The inductor DCR is important because the voltage dropped across it is proportional to the channel current. By using a simple R-C network and a current sense amplifier, as shown in Figure 5, the voltage drop across the inductor's DCR can be extracted. The output of the current sense amplifier, VDROOP, can be shown to be proportional to the channel current IL, shown in Equation 6.
V sL ------------- + 1 R COMP DCR ( s ) = ------------------------------------------------------------------------- ----------------------- ( I ) DCR DROOP L (s R C + 1) R COMP COMP S
(EQ. 6)
If the R-C network components are selected such that the R-C time constant matches the inductor L/DCR time constant, then VDROOP is equal to the voltage drop across
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the DCR, multiplied by a gain. As Equation 7 shows, VDROOP is therefore proportional to the total output current, IOUT.
R COMP V DROOP = -------------------- I OUT DCR RS (EQ. 7)
VDIFF
+ VOFS -
RFB
VREF E/A
By simply adjusting the value of RS, the load line can be set to any level, giving the converter the right amount of droop at all load currents. It may also be necessary to compensate for any changes in DCR due to temperature. These changes cause the load line to be skewed, and cause the R-C time constant to not match the L/DCR time constant. If this becomes a problem a simple negative temperature coefficient resistor network can be used in the place of RCOMP to compensate for the rise in DCR due to temperature. Note: An optional 10nF ceramic capacitor from the ISEN+ pin to the ISEN- pin is recommended to help reduce any noise affects on the current sense amplifier due to layout
ROFS
FB IOFS
+ OFS ISL6314 GND GND 0.3V +
1.6V
VCC
Output-Voltage Offset Programming
The ISL6314 allows the designer to accurately adjust the offset voltage by connecting a resistor, ROFS, from the OFS pin to VCC or GND. When ROFS is connected between OFS and VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (IOFS) to flow into the OFS pin and out of the FB pin, providing a negative offset. If ROFS is connected to ground, the voltage across it is regulated to 0.3V, and IOFS flows into the FB pin and out of the OFS pin, providing a positive offset. The offset current flowing through the resistor between VDIFF and FB will generate the desired offset voltage which is equal to the product (IOFS x RFB). These functions are shown in Figures 6 and 7. Once the desired output offset voltage has been determined, use the following formulas in Equations 8 and 9 to set ROFS: For Negative Offset (connect ROFS to VCC):
1.6 RFB R OFS = -------------------------V OFFSET (EQ. 8)
FIGURE 6. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING
VDIFF VOFS +
RFB
VREF E/A
FB IOFS
VCC + OFS ISL6314 GND 0.3V +
ROFS
1.6V
For Positive Offset (connect ROFS to GND):
0.3 RFB R OFS = -------------------------V OFFSET (EQ. 9)
VCC
FIGURE 7. NEGATIVE OFFSET OUTPUT VOLTAGE PROGRAMMING
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Dynamic VID
Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the ISL6314 to do this by making changes to the VID inputs. The ISL6314 is required to monitor the DAC inputs and respond to on-thefly VID changes in a controlled manner, supervising a safe output voltage transition without discontinuity or disruption. The DAC mode the ISL6314 is operating in determines how the controller responds to a dynamic VID change. INTEL DYNAMIC VID TRANSITIONS When in Intel VR11 mode the ISL6314 checks the VID inputs on the positive edge of an internal 5.5MHz clock. If a new code is established and it remains stable for three consecutive readings (0.36s to 0.54s), the ISL6314 recognizes the new code and changes the internal DAC reference directly to the new level. The Intel processor controls the VID transitions and is responsible for incrementing or decrementing one VID step at a time. In VR11 mode, the ISL6314 will immediately change the internal DAC reference to the new requested value as soon as the request is validated, which means the fastest recommended rate at which a bit change can occur is once every 1s. If the VID code is changed by more then one step at a time, the DAC will try to track it at a 5.5MHz step rate. This will likely cause an overcurrent or overvoltage fault. AMD DYNAMIC VID TRANSITIONS When running in AMD 5-bit or 6-bit modes of operation, the ISL6314 responds differently to a dynamic VID change. In the AMD modes the ISL6314 still checks the VID inputs on the positive edge of an internal 5.5MHz clock. In these modes the VID code can be changed by more than a 1-bit step at a time. If a new code is established and it remains stable for three consecutive readings (0.36s to 0.54s), the ISL6314 recognizes the change and begins slewing the DAC in 6.25mV steps at a stepping frequency of 345kHz until the VID and DAC are equal. Thus, the total time required for a VID change, tDVID, is dependent only on the size of the VID change (VVID). The time required for a ISL6314-based converter in AMD 5-bit DAC configuration to make a 1.1V to 1.5V reference voltage change is about 186s, as calculated using Equation 10.
V VID 1 t DVID = ------------------------- -------------------- 3 0.00625 345 x 10 (EQ. 10)
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on the FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the FB to the COMP pin. This current then flows through the feedback resistor, RFB, and can cause the output voltage to overshoot or undershoot at the end of the VID transition. In order to ensure the smooth transition of the output voltage during a VID change, a VID-on-the-fly compensation network is required. This network is composed of a resistor and capacitor in series, RDVC and CDVC, between the DVC and the FB pin, as shown in Figure 8.
RFB VDIFF IDVC CC CDVC DVC RDVC FB COMP IC RC
IDVC = IC
REF
x2
+
ERROR AMPLIFIER
CREF VDAC+RGND
ISL6314 INTERNAL CIRCUIT
FIGURE 8. VID-ON-THE-FLY COMPENSATION NETWORK
This VID-on-the-fly compensation network works by sourcing AC current into the FB node to offset the effects of the AC current flowing from the FB to the COMP pin during a VID transition. To create this compensation current the ISL6314 sets the voltage on the DVC pin to be 2x the voltage on the REF pin. Since the error amplifier forces the voltage on the FB pin and the REF pin to be equal, the resulting voltage across the series RC between DVC and FB is equal to the REF pin voltage. The RC compensation components, RDVC and CDVC, can then be selected to create the desired amount of compensation current. The amount of compensation current required is dependant on the modulator gain of the system, K1, and the error amplifier R-C components, RC and CC, that are in series between the FB and COMP pins. Use Equations 11, 12, and 13 below to calculate the RC component values, RDVC and CDVC, for the VID-on-the-fly compensation network. For these equations: VIN is the input voltage for the power train; VPP is the oscillator ramp amplitude (1.5V); and RC and CC are the error amplifier R-C components between the FB and COMP pins.
V IN K1 = ---------V PP K1 A = ---------------K1 - 1 (EQ. 11)
VID "OFF" DAC CODES Both the Intel VR11 and the AMD 5-bit VID tables include "Off" DAC codes, which indicate to the controller to disable all regulation. Recognition of these codes is slightly different in that they must be stable for four consecutive readings of a 5.5MHz clock (0.54s to 0.72s) to be recognized. Once an "Off" code is recognized the ISL6314 latches off, and must be reset by dropping the EN pin.
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R DVC = A x R C CC C DVC = ------A
1.6 1.4
(EQ. 12)
(EQ. 13)
CBOOT_CAP (F)
1.2 1. 0.8 0.6 QGATE = 100nC 0.4 50nC 0.2 20nC 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Advanced Adaptive Zero Shoot-Through Deadtime Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower MOSFET body-diode conduction, and to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off. During turn-off of the lower MOSFET, the PHASE voltage is monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor current). At this time the UGATE is released to rise. An auto-zero comparator is used to correct the rDS(ON) drop in the phase voltage preventing false detection of the -0.3V phase level during rDS(ON) conduction period. In the case of zero current, the UGATE is released after 35ns delay of the LGATE dropping below 0.5V. When LGATE first begins to transition low, this quick transition can disturb the PHASE node and cause a false trip, so there is 20ns of blanking time once LGATE falls until PHASE is monitored. Once the PHASE is high, the advanced adaptive shoot-through circuitry monitors the PHASE and UGATE voltages during a PWM falling edge and the subsequent UGATE turn-off. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V, the LGATE is released to turn-on.
0.0 0.0
VBOOT_CAP (V)
FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
The bootstrap capacitor must have a maximum voltage rating above PVCC + 4V and its capacitance value can be chosen from Equation 14: where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The VBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. Typical curves are shown in Figure 9.
Q GATE C BOOT_CAP ------------------------------------V BOOT_CAP Q G1 PVCC Q GATE = ---------------------------------- N Q1 V GS1 (EQ. 14)
Gate Drive Voltage Versatility
The ISL6314 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The controller ties the upper and lower drive rails together. Simply applying a voltage from 5V up to 12V on PVCC sets both gate drive rail voltages simultaneously.
Internal Bootstrap Device
The integrated driver features an internal bootstrap schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the PHASE node. This reduces voltage stress on the boot to phase pins.
Initialization
Prior to initialization, proper conditions must exist on the EN, VCC, PVCC and the VID pins. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, the controller asserts PGOOD.
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.
ISL6314 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
4. The VID code must not be 11111 in AMD 5-bit mode. This code signals the controller that no load is present. The controller will not allow soft-start to begin if this VID code is present on the VID pins. Once all of these conditions are met the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level.
VCC
PVCC
+12V
POR CIRCUIT
ENABLE COMPARATOR + EN
Intel Soft-Start
10.7k
1.40k 0.85V
The soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. The soft-start sequence for the Intel modes of operation is slightly different than the AMD soft-start sequence.
SOFT-START AND FAULT LOGIC
VOUT, 500mV/DIV
FIGURE 10. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
td1
td2 EN
td3
td4
td5
Enable and Disable
While in shutdown mode, the LGATE and UGATE signals are held low to assure the MOSFETs remain off. The following input conditions must be met, for both Intel and AMD modes of operation, before the ISL6314 is released from shutdown mode to begin the soft-start startup sequence: 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6314 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6314 will not inadvertently turn off unless the bias voltage drops substantially (see Electrical Specifications on page 6). 2. The voltage on EN must be above 0.85V. The EN input allows for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6314 in shutdown until the voltage at EN rises above 0.85V. The enable comparator has 110mV of hysteresis to prevent bounce. 3. The driver bias voltage applied at the PVCC pin must reach the internal power-on reset (POR) rising threshold. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6314 will not inadvertently turn off unless the PVCC bias voltage drops substantially (see Electrical Specifications on page 6). For Intel VR11 and AMD 6-bit modes of operation these are the only conditions that must be met for the controller to immediately begin the soft-start sequence, as shown in Figure 10. If running in AMD 5-bit mode of operation there is one more condition that must be met:
PGOOD 500s/DIV
FIGURE 11. INTEL SOFT-START WAVEFORMS
For the Intel VR11 mode of operation, the soft-start sequence is composed of four periods, as shown in Figure 11. Once the ISL6314 is released from shutdown and soft-start begins (as described in the "Enable and Disable" on page 20), the controller will have fixed delay period td1, typically 1.1ms. After this delay period, the VR will begin first soft-start ramp until the output voltage reaches 1.1V VBOOT voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period td3, typically 93s. At the end of td3 period, ISL6314 will read the VID signals. It is recommended that the VID codes be set no later then 50s into period td3. If the VID code is valid, ISL6314 will initiate the second soft-start ramp until the output voltage reaches the VID voltage plus/minus any offset or droop voltage. The soft-start time is the sum of the 4 periods as shown in Equation 15.
t SS = t d1 + t d2 + t d3 + t d4 (EQ. 15)
During td2 and td4, ISL6314 digitally controls the DAC voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor RSS from SS pin to GND. The
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second soft-start ramp time td2 and td4 can be calculated based on Equations 16 and 17:
t d2 = 1.1 R SS 8 10
-3
( s )
(EQ. 16)
Table 5 is a summary table of the typical soft-start timing for both modes. The times listed are fixed delays; the variable ones (defined by the equations) depend on the slope of the ramp (1.25 mV/s for a nominal 100k RSS resistor), and the amount of voltage excursion.
TABLE 5. ISL6314 SOFT_START TIMING SUMMARY MODE TIME SLOT td1 td2 td3 td4 td5 TIME 1.1ms EQ 16 93s EQ 17 93s
t d4 = V VID - 1.1 R SS 8 10
-3
( s )
(EQ. 17)
For example, when VID is set to 1.5V and the RSS is set at 100k, the first soft-start ramp time td2 will be 880s and the second soft-start ramp time td4 will be 320s. After the DAC voltage reaches the final VID setting, PGOOD will be set to high with the fixed delay td5. The typical value for td5 is 93s.
VR11 VR11 VR11 VR11 VR11
AMD Soft-Start
AMD AMD
VOUT, 500mV/DIV
tdA tdB
1.1ms EQ 18
Pre-Biased Soft-Start
OUTPUT PRECHARGED ABOVE DAC LEVEL tdA EN tdB OUTPUT PRECHARGED BELOW DAC LEVEL
PGOOD 500s/DIV
GND>
VOUT (0.5V/DIV)
FIGURE 12. AMD SOFT-START WAVEFORMS
GND> EN (5V/DIV)
For the AMD 5-bit and 6-bit modes of operation, the soft-start sequence is composed of two periods, as shown in Figure 12. At the beginning of soft-start, the VID code is immediately obtained from the VID pins, followed by a fixed delay period tdA of typically 1.1ms. After this delay period the ISL6314 will begin ramping the output voltage to the desired DAC level at a fixed rate of 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor RSS on the SS pin. The amount of time required to ramp the output voltage to the final DAC voltage is referred to as tdB, and can be calculated as shown in Equation 18.
8 10 t dB = V VID R SS
-3
T1 T2
T3
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6314-BASED CONVERTER
( s )
(EQ. 18)
At the end of soft-start, PGOOD will immediately go high if the VSEN voltage is within the undervoltage and overvoltage limits.
The ISL6314 also has the ability to start up into a pre-charged output, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off. Once the internal ramping reference exceeds the FB pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged level to the final level dictated by the DAC setting. Should the output be pre-charged to a level exceeding the DAC setting, the output drives are enabled at the end of the soft-start period, leading to an abrupt correction in the output voltage down to the DAC-set level. See Figure 13.
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ISL6314 Fault Monitoring and Protection
The ISL6314 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 14 outlines the interaction between the fault monitors and the power good signal.
ROCSET ISENO ISEN+
code, the controller latches off and PGOOD will not return high until EN is toggled and a successful soft-start is completed. In the case of an undervoltage event, PGOOD will return high when the output voltage rises above the undervoltage hysteresis level. PGOOD is always low prior to the end of soft-start. For AMD modes of operation, PGOOD will always be high as long as VSEN is within the specified undervoltage/ overvoltage window and soft-start has ended. PGOOD only goes low if VSEN is outside this window. Even if the controller is shut down the PGOOD signal will still stay high until VSEN falls below the undervoltage threshold.
-
VOCSET
+
OCSET
+ ISENISEN
VDROOP 100A
Overvoltage Protection
The ISL6314 constantly monitors the difference between the VSEN and RGND voltages to detect if an overvoltage event occurs. During soft-start, while the DAC is ramping up, the overvoltage trip level is the higher of a fixed voltage 1.27V or DAC + 175mV for Intel modes of operation and DAC + 225mV for AMD modes of operation. Upon successful soft-start, the overvoltage trip level is only DAC + 175mV or DAC + 225mV depending on whether the controller is running in Intel or AMD mode. When the output voltage rises above the OVP trip level actions are taken by the ISL6314 to protect the microprocessor load. At the inception of an overvoltage event, LGATE is commanded high and the PGOOD signal is driven low. This turns on the lower MOSFETs and pulls the output voltage below a level that might cause damage to the load. The LGATE output remains high until VSEN falls 100mV below the OVP threshold that tripped the overvoltage protection circuitry. The ISL6314 will continue to protect the load in this fashion as long as the overvoltage condition recurs. Once an overvoltage condition ends, the ISL6314 latches off, and must be reset by toggling EN, or through POR, before a soft-start can be reinitiated. There is an OVP condition that exists that will not latch off the ISL6314. During a soft-start sequence, if the VSEN voltage is above the OVP threshold an overvoltage event will occur, but will be released once VSEN falls 100mV below the OVP threshold. If VSEN then rises above the OVP trip threshold a second time, the ISL6314 will be latched off and cannot be restarted until the controller is reset.
+ +
OC
-
VDIFF +1V
+ -
VID + OFFSET mV
SOFT-START, FAULT AND CONTROL LOGIC VOVP
VSEN
+
x1
+ +
OV PGOOD
RGND
UV
VID - OFFSET mV ISL6314 INTERNAL CIRCUITRY
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output that signals whether or not the ISL6314 is regulating the output voltage within the proper levels, and whether any fault conditions exist. This pin should be tied through a resistor to a voltage source that's equal to or less than VCC. For Intel mode of operation, PGOOD indicates whether VSEN is within specified overvoltage and undervoltage limits after a fixed delay from the end of soft-start. PGOOD transitions low when an undervoltage, overvoltage, or overcurrent condition is detected or when the controller is disabled by a reset from EN, POR, or one of the no-CPU VID codes. In the event of an overvoltage or overcurrent condition, or a no-CPU VID
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the ISL6314 is designed to protect the load from any overvoltage events that may occur. This is accomplished by means of an internal 10k resistor tied from PHASE to LGATE, which turns on the lower MOSFET to control the output voltage until the overvoltage event ceases or the input power supply cuts off. For complete protection, the low side MOSFET should have a gate threshold well below the maximum voltage rating of the load/microprocessor. In the event that during normal operation the PVCC or VCC voltage falls back
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ISL6314
below the POR threshold, the pre-POR overvoltage protection circuitry reactivates to protect from any more prePOR overvoltage events. soft-start can be reinitiated. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. Figure 15 shows an example.
Undervoltage Detection
The undervoltage threshold is set at DAC - 350mV of the VID code. When the output voltage (VSEN - RGND) is below the undervoltage threshold, PGOOD gets pulled low. No other action is taken by the controller. PGOOD will return high if the output voltage rises above DAC - 250mV.
OUTPUT CURRENT, 25A/DIV
Open Sense Line Protection
In the case that either of the remote sense lines (VSEN or RGND) become open, the ISL6314 is designed to prevent the controller from regulating. This is accomplished by means of a small 5A pull-up current on VSEN, and a pull-down current on RGND. If the sense lines are opened at any time, the voltage difference between VSEN and RGND will increase until an overvoltage event occurs, at which point overvoltage protection activates and the controller stops regulating. The ISL6314 will be latched off and cannot be restarted until the controller is reset.
0A
OUTPUT VOLTAGE, 500mV/DIV
0V 1ms/DIV
FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE
Overcurrent Protection
The ISL6314 detects overcurrent events by comparing the droop voltage, VDROOP, to the OCSET voltage, VOCSET, as shown in Figure 14. The droop voltage, set by the external current sensing circuitry, is proportional to the output current as shown in Equation 19. A constant 100A flows through ROCSET, creating the OCSET voltage. When the droop voltage exceeds the OCSET voltage, the overcurrent protection circuitry activates. Since the droop voltage is proportional to the output current, the overcurrent trip level, IMAX, can be set by selecting the proper value for ROCSET, as shown in Equation 20.
R COMP V DROOP = -------------------- I OUT DCR RS I MAX R COMP DCR R OCSET = --------------------------------------------------------100A R S (EQ. 19)
General Design Guide
This design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.
Power Stage
The first step in designing a power converter using the ISL6314 is to determine if one phase is sufficient (if not, Intersil offers other parts, such as the ISL6313, which has two phases with similar features). This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. Generally speaking, the most economical solutions are those in which the output handles between 25A and 30A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat-dissipating surfaces.
(EQ. 20)
Once the output current exceeds the overcurrent trip level, VDROOP will exceed VOCSET, and a comparator will trigger the converter to begin overcurrent protection procedures. At the beginning of an overcurrent shutdown, the controller turns off both upper and lower MOSFETs and lowers PGOOD. The controller will then immediately attempt to soft-start (which includes the 1.1ms delay of either td1 or tdA). If the overcurrent fault remains, the trip-retry cycles will continue until either the controller is disabled or the fault is cleared. But if five overcurrent events occur without successfully completing soft-start, the controller will latch off after the fifth try and must be reset by toggling EN before a
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MOSFETS The choice of MOSFETs depends on the current each MOSFET will be required to conduct, the switching frequency, the capability of the MOSFETs to dissipate heat, and the availability and nature of heat sinking and air flow. LOWER MOSFET POWER CALCULATION The calculation for power loss in the lower MOSFET is simple, since virtually all of the loss in the lower MOSFET is due to current conducted through the channel resistance (rDS(ON)). In Equation 21, IM is the maximum continuous output current, IPP is the peak-to-peak inductor current (see Equation 1), and d is the duty cycle (VOUT/VIN).
I L ( PP )2 ( 1 - d ) I M 2 P LOW ( 1 ) = r DS ( ON ) ----- ( 1 - d ) + -------------------------------------12 N (EQ. 21)
At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 24, the approximate power loss is PUP(2)..
I M I PP t 2 P UP ( 2 ) V IN ----- - -------- ---- f S 2 2 N (EQ. 24)
A third component involves the lower MOSFET reverserecovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lowerMOSFET body diode can recover all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP(3), as shown in Equation 25.
P UP ( 3 ) = V IN Q rr f S (EQ. 25)
An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lowerMOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON), the switching frequency, fS, and the length of dead times, td1 and td2, at the beginning and the end of the lower-MOSFET conduction interval respectively.
I I I M I PP P LOW ( 2 ) = V D ( ON ) f S ------ + --------- t + M PP t d1 ------ - --------- d2 2 N 2 N
Finally, the resistive part of the upper MOSFET is given in Equation 26 as PUP(4)..
I PP2 I M P UP ( 4 ) r DS ( ON ) d ----- + --------12 N
2
(EQ. 26)
(EQ. 22)
The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 23, 24, 25 and 26. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies.
Note that the dead times td1 and td2 in Equation 22 are NOT related to the soft-start timing delays. The total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW(1) and PLOW(2). UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverse-recovery charge, Qrr, and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 23, the required time for this commutation is t1 and the approximated associated power loss is PUP(1)..
I M I PP t 1 P UP ( 1 ) V IN ----- + -------- ---- f S N2 2 (EQ. 23)
Package Power Dissipation
When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there is one set of drivers in the controller package, the total power dissipated by it must be less than the maximum allowable power dissipation for the QFN package. Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125C. The maximum allowable IC power dissipation for the 5x5 QFN package is approximately 3W at room temperature. See "Layout Considerations" on page 29 for thermal transfer improvement suggestions. When designing the ISL6314 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, PQg_TOT, due to the gate charge of MOSFETs and the integrated driver's internal circuitry and their corresponding average driver current can be estimated with Equations 27 and 28, respectively.
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.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q VCC 3 P Qg_Q1 = -- Q G1 PVCC F SW N Q1 2 P Qg_Q2 = Q G2 PVCC F SW N Q2 3 + Q G2 N Q2 F SW + I Q I DR = -- Q G1 N 2 Q1
(EQ. 27)
the MOSFETs. Figures 16 and 17 show the typical upper and lower gate drives turn-on transition path. The total power dissipation in the controller itself, PDR, can be roughly estimated as shown in Equation 29.:
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q VCC ) P Qg_Q1 P BOOT = --------------------3 (EQ. 29)
(EQ. 28)
R HI1 R LO1 P Qg_Q1 P DR_UP = -------------------------------------- + --------------------------------------- --------------------R HI1 + R EXT1 R LO1 + R EXT1 3 R HI2 R LO2 P Qg_Q2 P DR_LOW = -------------------------------------- + --------------------------------------- --------------------2 R HI2 + R EXT2 R LO2 + R EXT2 R GI1 R EXT1 = R G1 + ------------N
Q1
In Equations 27 and 28, PQg_Q1 is the total upper gate drive power loss and PQg_Q2 is the total lower gate drive power loss; the gate charge (QG1 and QG2) is defined at the particular gate to source drive voltage PVCC in the corresponding MOSFET data sheet; IQ is the driver total quiescent current with no load at both drive outputs; NQ1 and NQ2 are the number of upper and lower MOSFETs respectively. The IQ*VCC product is the quiescent power of the controller without capacitive load and is typically 75mW at 300kHz.
PVCC BOOT D CGD RHI1 RLO1 UGATE G RG1 RGI1 CGS S PHASE Q1 CDS
R GI2 R EXT2 = R G2 + ------------N
Q2
Inductor DCR Current Sensing Component Selection
For accurate load line regulation, the ISL6314 senses the total output current by detecting the voltage across the output inductor DCR (as described in the "Load-Line (Droop) Regulation" on page 16). As Figure 18 illustrates, an R-C network is required to accurately sense the inductor DCR voltage and convert this information into a "droop" voltage, which is proportional to the total output current.
L PHASE DCR VOUT COUT VL(s) + IOUT
INDUCTOR I L RS
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
ISENPVCC + D CGD RHI2 RLO2 LGATE G RG2 RGI2 CGS S Q2 ISL6314 CDS CCOMP ISENO VDROOP + ISEN+ (optional)
RCOMP
FIGURE 18. DCR SENSING CONFIGURATION FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, PDR_UP, the lower drive path resistance, PDR_UP, and in the boot strap diode, PBOOT. The rest of the power will be dissipated by the external gate resistors (RG1 and RG2) and the internal gate resistors (RGI1 and RGI2) of
Choosing the components for this current sense network is a two step process. First, RCOMP and CCOMP must be chosen so that the time constant of this RCOMP - CCOMP network matches the time constant of the inductor L/DCR. Then the resistor RS must be chosen to set the current sense network gain, obtaining the desired full load droop voltage. Follow the steps below to choose the component values for this R-C network.
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1. Choose an arbitrary value for CCOMP. The recommended value is 0.01F. 2. Plug the inductor L and DCR component values, and the values for CCOMP chosen in steps 1, into Equation 30 to calculate the value for RCOMP.
L R COMP = --------------------------------------DCR C COMP (EQ. 30)
Loadline Regulation Resistor
If loadline regulation is desired, the resistor on the FS pin, RT, should be connected to Ground (the value of RT separately selects the switching frequency, as per Equation 42). The desired loadline, RLL, can be calculated by Equation 33 where VDROOP is the desired droop voltage at the full load current IFL.
V DROOP R LL = -----------------------I FL (EQ. 33)
3. Use the new value for RCOMP obtained from Equation 30, as well as the desired full load current, IFL, full load droop voltage, VDROOP, and inductor DCR in Equation 31 to calculate the value for RS.
I FL R S = ------------------------ R COMP DCR V DROOP (EQ. 31)
Based on values for Equation 31, the desired loadline can also be calculated from Equation 34.
R COMP DCR R LL = --------------------------------------RS (EQ. 34)
Due to errors in the inductance or DCR it may be necessary to adjust the value of R1 to match the time constants correctly. The effects of time constant mismatch can be seen in the form of droop overshoot or undershoot during the initial load transient spike, as shown in Figure 19. Follow the steps below to ensure the R-C and inductor L/DCR time constants are matched accurately. 1. Capture a transient event with the oscilloscope set to about L/DCR/2 (sec/div). For example, with L = 1H and DCR = 1m, set the oscilloscope to 500s/div. 2. Record V1 and V2 as shown in Figure 19. 3. Select new values, R1,NEW, for the time constant resistor based on the original value, R1,OLD, using Equation 32.
V 1 R 1, NEW = R 1, OLD ---------V 2 (EQ. 32)
If no loadline regulation is required, the resistor on the FS pin, RT, should be connected to the VCC pin (the value of RT separately selects the switching frequency, as per Equation 42).
APA Pin Component Selection
A 100A current flows out of the APA pin and across RAPA to set the APA trip level. A 1000pF capacitor, CAPA, should also be placed across the RAPA resistor to help with noise immunity. An APA trip level of 500mV is recommended for most applications. Use Equation 35 below to set RAPA to get the desired APA trip level.
V APA, TRIP 500mV R APA = ------------------------------ = ---------------------------- = 5k 100 x 10 - 6 100 x 10 - 6 (EQ. 35)
4. Replace R1 with the new value and check to see that the error is corrected. Repeat the procedure if necessary.
Compensation
The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals.
VOUT
V2 V1
COMPENSATION WITH LOAD-LINE REGULATION The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the output filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, RC and CC, as shown in Figure 20.
ITRAN I
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
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C2 (OPTIONAL)
Case 1:
RC CC COMP
1 ------------------------------- > f 0 2 LC 2 f 0 V pp L C R C = R FB ------------------------------------------------------V
IN
FB
ISL6314
RFB VDIFF
V IN C C = --------------------------------------------------2 V PP R FB f 0
Case 2:
FIGURE 20. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6314 CIRCUIT
1 1 ------------------------------- f 0 < -----------------------------------2 C ESR 2 LC V PP ( 2 ) 2 f 02 L C R C = R FB ---------------------------------------------------------------V
IN
(EQ. 36)
Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the switching frequency. The values of the compensation components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the compensation components. In Equation 36, L is the filter inductance; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in the Electrical Specifications on page 6. Once selected, the compensation values in Equation 36 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the value of RC while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from Equation 36 unless some performance issue is noted.
V IN C C = ------------------------------------------------------------------------------------2 f 2 V (2 ) 0 PP R FB L C
Case 3:
1 f 0 > -----------------------------------2 C ESR 2 f 0 V pp L R C = R FB ------------------------------------------V ESR
IN
V IN ESR C C C = ---------------------------------------------------------------2 V PP R FB f 0 L
The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 20). Keep a position available for C2, and be prepared to install a highfrequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted. For the solutions in equation 36, RFB is selected arbitrarily, typically in the 1k to 5k range. COMPENSATION WITHOUT LOAD-LINE REGULATION The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 21, provides the necessary compensation. The first step is to choose the desired bandwidth, f0, of the compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, fHF. This pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose fHF = 10f0, but it can be higher if desired. Choosing fHF to be lower than 10f0 can cause problems with too much phase shift below the system bandwidth.
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C2
RC
CC
COMP
FB C1 R1 RFB VDIFF
ISL6314
In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, I, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, Equation 38 shows the output voltage initially deviates by an amount
di V ESL ---- + ESR I dt (EQ. 38)
FIGURE 21. COMPENSATION CIRCUIT WITHOUT LOAD-LINE REGULATION
.
C ESR R 1 = R FB ------------------------------------------L C - C ESR L C - C ESR C 1 = ------------------------------------------R FB V IN C 2 = --------------------------------------------------------------------------------------------------2f f (2 ) 0 HF ( L C ) R FB V PP (EQ. 37) V PP 2 f 0 f HF L C R FB R C = ---------------------------------------------------------------------------------------V ( 2 f HF L C - 1 )
IN 2
The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see "Output Ripple" on page 10 and Equation 39), a voltage develops across the bulk capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance.
V - V OUT V OUT IN L ESR --------------------------------------------------------f S V IN V PP( MAX ) (EQ. 39)
V IN ( 2 f HF L C - 1 ) C C = --------------------------------------------------------------------------------------------------( 2 ) 2 f 0 f HF ( L C ) R FB V PP
In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 37, RFB is selected arbitrarily, typically in the 1k to 5k range. The remaining compensation components are then selected according to Equation 37. In Equation 37, L is the filter inductance; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in Electrical Specifications on page 6.
Output Filter Design
The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductor increases or decreases to meet the demand.
Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductor must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limit on inductance. Equation 40 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 41
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addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the inductance, and C is the total output capacitance.
2 C VO L ------------------------ V MAX - ( I ESR ) ( I ) 2 (EQ. 40)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the ac component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. Use Figure 23 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (IO), and the ratio of the peak-to-peak inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage.
.
1.25 C L ------------------- V MAX - ( I ESR ) V IN - V O ( I ) 2
(EQ. 41)
Switching Frequency
There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in MOSFETs, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage ripple. Choose the lowest switching frequency that allows the regulator to meet the transientresponse requirements. Switching frequency is determined by the selection of the frequency-setting resistor, RT. Figure 22 and Equation 42 are provided to assist in selecting the correct value for RT.
R T = 10 [10.61 - ( 1.035 log ( f S ) ) ] (EQ. 42)
0.6 INPUT-CAPACITOR CURRENT (IRMS/IO)
0.4
0.2
IL(PP) = 0 IL(PP) = 0.5 IO IL(PP) = 0.75 IO
0 0 0.2 0.4 0.6 0.8 1.0
500
DUTY CYCLE (VIN/VO)
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR SINGLE-PHASE CONVERTER
RT (k) 100
10 50
100
1000 SWITCHING FREQUENCY (kHz)
2000
Low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component selection, layout, and placement minimizes these voltage spikes. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path
FIGURE 22. RT vs SWITCHING FREQUENCY
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ISL6314
generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. There are two sets of critical components in a DC/DC converter using a ISL6314 controller. The power components are the most critical because they switch large amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. The power components should be placed first, which include the MOSFETs, input and output capacitors, and the inductor. Keep the gate drive traces short, resulting in low trace impedances. When placing the MOSFETs try to keep the source of the upper FETs and the drain of the lower FETs as close as thermally possible. Input Bulk capacitors should be placed close to the drain of the upper FETs and the source of the lower FETs. Locate the output inductor and output capacitors between the MOSFETs and the load. The high-frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND next to, or on the capacitor solder pad. The critical small components include the bypass capacitors for VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC and PVCC bypass capacitors as close to the ISL6314 as possible. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to EMI pick-up. A multi-layer printed circuit board is recommended. Figure 24 shows the connections of the critical components for the converter. Note that capacitors CxxIN and CxxOUT could each represent numerous physical capacitors. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase node. Use the remaining printed circuit layers for small signal wiring. impedance and inductance. They should be sized to carry at least one ampere of current (0.02" to 0.05"). Going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibility of shoot-through. It is also important to route each channels UGATE and PHASE traces in as close proximity as possible to reduce their inductances.
Current Sense Component Placement and Trace Routing
One of the most critical aspects of the ISL6314 regulator layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISEN+ and ISEN- pins on the ISL6314 as possible. The sense traces that connect the R-C sense components to each side of the output inductors should be routed on the bottom of the board, away from the noisy switching components located on the top of the board. These traces should be routed side by side, and they should be very thin traces. It's important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible.
Thermal Management
For maximum thermal performance in high current, high switching frequency applications, connecting the thermal GND pad of the ISL6314 to the ground plane with multiple vias is recommended. This heat spreading allows the part to achieve its full thermal potential. It is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part.
Routing UGATE, LGATE, and PHASE Traces
Great attention should be paid to routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall
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ISL6314
RFB C2 R2
LOCATE CLOSE TO IC (MINIMIZE CONNECTION PATH)
RDVC CDVC
FB DVC VDIFF VSEN RGND
KEY HEAVY TRACE ON CIRCUIT PLANE LAYER ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER
C1 C3 R1
COMP
VIA CONNECTION TO GROUND PLANE
CAPA
APA
RAPA
+5V VCC
(CF1) ROFS
OFS FS
LOCATE NEAR SWITCHING TRANSISTORS; (MINIMIZE CONNECTION PATH)
+12V PVCC
RT CREF
REF
(CF2) CBOOT
BOOT
CBIN (CHFIN) CBOUT(CHFOUT)
SS
UGATE PHASE
RSS
ISL6314
LGATE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 LOAD
LOCATE NEAR LOAD; (MINIMIZE CONNECTION PATH)
PGOOD
EN
GND ISEN+ OCSET ISENO ISEN-
ROCSET
CCOMP RS RCOMP
FIGURE 24. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
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ISL6314 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 3.15 3.15 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 5.00 BSC 4.75 BSC 3.30 5.00 BSC 4.75 BSC 3.30 0.50 BSC 0.40 32 8 8 0.60 12 0.50 0.15 3.45 3.45 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 32
FN6455.0 March 30, 2007

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